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System-Management IC with Programmable Quad Voltage Monitoring and Supervisory Functions
Preliminary Technical Data
FEATURES
* Two Device-Enabling Outputs with Six Programmable Monitoring Inputs (Table 1) o Two 30V Monitoring Inputs with Shutdown Control of External Devices: Programmable Over-voltage, Under-voltage, Turn-on, Turn-off Thresholds, and Shutdown timings
AD5100
APPLICATIONS
* * * Automotive Systems Network Equipment Computers, Controllers, and Embedded Systems
GENERAL DESCRIPTION
The AD5100 is a programmable system-management IC that combines 4-channel of voltage monitoring and a watchdog supervision that can be used to shutdown external supplies, reset processors, or disable any other system electronics when the systems malfunction. The AD5100 can also be used to protect system under faulty condition of improper devices power up sequencing. The AD5100 can monitor two 30V inputs with shutdown and reset controls, one 2.5V-5.0V and one 0.9V3.3V monitoring inputs with reset control, a robust watchdog reset controller. Most monitoring input thresholds and timing settings can be programmed on the fly or permanently set in the factory with the OTP feature. The AD5100 is versatile for system-monitoring applications where critical P, DSP, and embedded systems operate under harsh conditions such as automotive, industrial, or communications network environments. The AD5100 is available in compact QSOP-16 and can operate in an extended automotive temperature range from -40oC to +125oC.
1 2
Shutdown Warning with Fault Detection
o Two 5V Monitoring Inputs with Reset Control of External Devices: Programmable Reset Thresholds and Hold Time o Two Supervisory Functions: Watchdog Reset Controller with Programmable Timeout and Selectable Floating Input Manual Reset Control for External Devices * Digital Interface and Programmability: o I2C Compatible Interface o OTP1 for Permanent Threshold and Timing Settings o OTP Overwritten Capable for Dynamic Adjustments o Power Up by Edge Triggered Signal o Power Down by I2C Software * Operating Range: o Supply Voltage 6.0V to 30V o Temp Range -40oC to +125oC o Low Shutdown Current: 10A * High-Voltage-Input Anti-migration Shielding Pinouts
(R)
.One Time Programmable EPROM - Unlimited Adjustment Before OTP Execution. With Programmable Threshold and Programmable Delay.
Table 1. AD5100 General Inputs and Output Information
Input Monitoring Range2 Shutdown Control Reset Cont rol Fault Dete ctio n
V1MON V2MON V3MON V4MON WDI
6 - 30 V 3 - 30 V 2.5 - 5.0 V 0.9 - 3.3 V 0-5V 0-5V

MR
Rev. PrJ
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD5100
FUNCTIONAL BLOCK DIAGRAM
Preliminary Technical Data
Figure 1. Functional Block Diagram
Rev. PrJ | Page 2 of 32
Preliminary Technical Data
AD5100
Electrical Characteristics
6V V1MON 30V and 3V V2MON 30V, -40C TA +125C, unless otherwise noted. Table 2.
Parameter Symbol Conditions HIGH-VOLTAGE MONITORING INPUTS V1MON, V2MON AND SHDN , SHDNWARN OUTPUT Input Resistance V1MON OV, UV Threshold Tolerance (Figure 5 and Table 5a) Hysteresis Programmable Shutdown Hold Time Tolerance (Figure 5 and Table 6a) Programmable Shutdown Delay Tolerance (Figure 4 and Table 6a) Fault Detection Delay Glitch-Immune Time V2MON On, Off Threshold Tolerance2 (Figure 5 and Table 5a) Hysteresis Turn-On Programmable SHDN Hold Time Tolerance (Figure 5 and Table 6a) Turn-Off Programmable SHDN Delay Time Tolerance (Figure 5 and Table 6a) Fault Detection Delay Glitch Immune Time SHDN SHDN Output High SHDN Output High SHDN Output Low SHDN Output Low SHDN Sink Current SHDNWARN (Open Drain Output) SHDNWARN Inactive Leakage Current SHDNWARN Active Voltage Range Input Resistance V3MON, V4MON V3MON Threshold Tolerance (Figure 6 and Table 5a) RIN_V1MON, RIN_V2MON OV, UV TA = 25oC TA = -40oC to 85oC TA = -40oC to 125oC Does not apply to code 0x7 -1.5 -2 -3 1.5 t1SD_HOLD -10 +10 Min Typ1 60 +1.5 +2 +3 Max Unit K % % % % %
t1SD_DELAY
Does not apply to code 0x7
-10
+10
%
tFD_DELAY tGLITCH On, Off TA = 25oC TA = -40oC to 85oC TA = -40oC to 125oC Does not apply to code 0x7 -1.5 -2 -3
70 50 +1.5 +2 +3 1.5 +10
s s % % % % %
t2SD_HOLD
-10
t2SD_DELAY
Does not apply to code 0x7
-10
+10
%
tFD_DELAY tGLITCH VOH VOH VOL VOL ISINK IOH_SHDNWARN VOL_SHDNWARN V3MON, V4MON RIN_V1MON, RIN_V2MON V3MON
V2MON_OFF only
70 50 2.4 V1MON-0.5 1.7 10 1 0.4 3 15
s s V V V V mA A 0.4 V V K % % % %
VRAIL=VREG, ISOURCE=40uA VRAIL=V1MON, ISOURCE=600uA ISINK=1.6mA V1MON=12V, ISINK=40mA V1MON=12V, SHDN forced to 12V
Isink = 3mA -0.3 50 TA = 25oC TA = -40oC to 85oC TA = -40oC to 125oC -1.5 -2 -3 1.5
Rev. PrJ | Page 3 of 32
LOW-VOLTAGE MONITORING INPUTS V3MON, V4MON AND RESET OUTPUT 5.5
+1.5 +2.7 +3.5
V3MON Hysteresis
V3_HYSTERESIS
AD5100
Parameter V4MON Threshold Tolerance (Figure 7 and Table 5a) V4MON Hysteresis Reset Hold Time Tolerance (Figures 6, 7, and Table 6a) V3,4MON-to-RESET Delay RESET Output Voltage Symbol V4MON Conditions TA = 25oC TA = -40oC to 85oC TA = -40oC to 125oC Does not apply to codes 0x6 and 0x7
Preliminary Technical Data
Min -2.5 -3 -3.5 -10 70 V3MON 4.38V, ISOURCE = 120uA 2.7V < V3MON 4.38V, ISOURCE = 30uA 2.3V < V3MON 2.7V, ISOURCE = 20uA 1.8V V3MON 2.3V, ISOURCE = 8uA V3MON > 4.38V, ISINK = 3.2mA V3MON < 4.38V, ISINK = 1.2mA RESET = 0, V3MON = 5.5V RESET = 0, V3MON = 3.6V V3MON-1.5 0.8xV3MON 0.8xV3MON 0.8xV3MON 0.4 0.3 800 400 50 Open Drain Apply to RESET disabled only -10 70 10 +10 5.5 Typ1 Max +2.5 +3 +3.5 +10 Unit % % % % % s V V V V V V A A s V s KHz %
V4_HYSTERESIS tRS_HOLD tRS_DELAY VOH
6
VOL RESET Output Short-Circuit Current3 Glitch Immune Time V4OUT Maximum Output V4OUT Propagation Delay V4OUT Maximum Frequency WDI (WATCHDOG INPUT) WDI Programmable-Timeout Tolerance (Figure 8 and Table 6a) WDI Pulse Width Watchdog-Initiated RESET Pulse Width Watchdog-Initiated SHDN WDI Input Voltage WDI Input Current MR (MANUAL RESET) INPUT MR Input Voltage MR Pulse Width MR Deglitching MR -to-Reset Delay MR Pullup Resistance (internal to V3MON) Reset Hold-Time Tolerance (Figure 9 and Table 6a) SERIAL INTERFACES VIL_MR VIH_MR tMR tMR_GLITCH tMR_DELAY ISOURCE
tGLITCH V4OUT_MAX tV4OUT_Delay fV4OUT tWD
tWDI tWDR tWD_SHDN VIL_WD VIH_WD
50 When no WDI When no WDI activity > 4 tWD 0.7xV3MON WDI = V3MON, time average WDI = 0, time average 160 -20 0.3*V3MON 0.7*V3MON 1 100 1 50 Do not apply to codes 0x6 and 0x7 -10 +10 tWD/50 1 0.3xV3MON
ns ms s V V A A V V s ns s K %
tRS_HOLD
Input Logic High (SCL, SDA)4 Input Logic Low (SCL, SDA)
Output Logic High (SDA) Output Logic Low (SDA) Input Capacitance POWER SUPPLY Supply Voltage Range
VIH VIL
VOH VOL CI V1MON
External Rpull-up = 2.2k External Rpull-up = 2.2k VRAIL = 3.3V, External Rpull-up = 2.2k VRAIL = 3.3V, External Rpull-up = 2.2k
2.0 0 3.0 0 5 6.0
5.5 0.8 3.3 0.4
V V
V V pF
30
V
Rev. PrJ | Page 4 of 32
Preliminary Technical Data
Parameter Sleep Mode Supply Current Active Mode Supply Current Symbol ISLEEP_V1MON IPOWER_V1MON Conditions V2MON = 0 V V2MON = 12 V V2MON Edge Triggered Mode Selected Min Typ1
AD5100
Max 10 3 3 Unit A mA mA V V ms s s V mA ms s
Device Power On Threshold Device Power Up V2MON Minimum Pulse Width (Figure 14) Device Power Down Delay OTP Supply Voltage6 OTP Supply Current OTP Settling Time7 TIMING CHARACTERISTICS 8 Parameter Adjustment Time I2C Interface Timing Characteristics SCL Clock Frequency tBUF Bus Free Time between Start and Stop tHD;STA Hold Time after (Repeated) START condition. After this period, the first clock is generated tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition
Notes: 1. 2. 3. 4. 5. 6. 7. 8.
V2MON,IH V2MON,IL tV2MON_PW V2MON < 0.4V (Normal Mode) I2C Initiated Power Down For OTP only For OTP only
2.2 0.4 4 2 10 6 200 12 1 6.5
VOTP IVOTP tS_OTP tS1
fSCL t1 t2
400 1.3 0.6
KHz s s
t3 t4 t5 t6 t7 t8 t9 t10
1.3 0.6 0.6
50
s s s s s s s s
0.9 0.1 0.3 0.3 0.6
Represent typical values at 25C, V1MON = 12 V, and V2MON = 12 V. Does not apply if V2MON is a digital signal. The RESET short-circuit current is the maximum pullup current when RESET is driven low by a P bidirectional reset pin. It is typical for the SCL and SDA have resistors to be pulled up to V3MON. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors. Initial V2MON ON minimum remains as 2.2V but the -0.3V to 30V specifications apply afterwards. VOTP can be furnished by Factory 6V power supply, rather than on-board power supply, when performing factory programming. A 10uF tantalum capacitor is required on VOTP during operation regardless of whether the OTP fuses are programmed. The OTP settling time occurs only once if OTP function is used. Guaranteed by design and not subject to production test.
t8
SCL
t6
t9
t2
t2
t3 t8 t9
t4
t7
t5
t10
SDA
t1
P S S P
Figure 2. Digital Interface Timing Diagram
Rev. PrJ | Page 5 of 32
04104-0-044
AD5100
Preliminary Technical Data
Absolute Maximum Ratings
Table 3.
Parameter V1MON to GND V2MON to GND V3MON to GND V4MON to GND VOTP to GND Digital Input Voltage to GND (MR , WDI, SCL, SDA, AD0) Digital Output Voltage to GND (RESET ,V4OUT, SHDNWARN ) Digital Output Voltage to GND (SHDN ) Operating Temperature Range HBM ESD (All Pins) Maximum Junction Temperature (TJmax) Storage Temperature Lead Temperature (Soldering, 10 s - 30 s) Thermal Resistance Junction-toAmbient1 JA Thermal Resistance Junction-to-Case JC
1
Rating -0.3 V, +33 V -0.3 V, +33 V -0.3 V, +7 V -0.3 V, +7 V -0.3 V, +7 V 0 V, +7V 0 V, +7V 0 V, +33V -40C to +125C 2KV 140C -65C to +150C 245C 105oC/W 39oC/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Package power dissipation = (TJmax - TA) / JA.
Rev. PrJ | Page 6 of 32
Preliminary Technical Data PIN CONFIGURATION AND FUNCTIONAL DESCRIPTION
V1MON 1 GND VOTP V3MON MR WDI SCL SDA 2 3 4 5 6 7 8 AD5100 16 V2MON 15 GND/NC 14 V4MON 13 AD0 12 SHDN 11 SHDNWARN 10 V4OUT 9 RESET
AD5100
Figure 3a. AD5100 Pin Configuration
GND
1 2 3 4 5 6 7 8 16 15 14
AD5100
13 12 11 10 9
Figure 3b. Recommended PCB Layout for Shielded High-Voltage Inputs
Table 4. AD5100 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic V1MON GND VOTP V3MON MR WDI SCL SDA RESET V4OUT SHDNWARN SHDN AD0 V4MON GND/NC V2MON Description High-voltage monitoring input. AD5100 internal supply is derived from V1MON.. Ground. One-time supply voltage for EPROM. Can be floating when it is not performing fuse programming Low-voltage monitoring-input Manual-Reset Input. Active-low. Watch-Dog Input. I2C Serial-Input Register Clock. If it is driven directly from a logic driver without the pull-up resistor, ensure that VIH min is 3.3V. I2C Serial Data Input/Output. If it is driven direct from a logic driver without the pull-up resistor, ensure that VIH min is 3.3V. RESET , Push-Pull Output with rail voltage of V3MON Open-drain output. Triggered by V4MON Shutdown Warning. Active-Low, Open-drain output. Shutdown output. Push-Pull Output with selectable rail voltage of V1MON or VREG . 30V maximum I2C Slave-Address Configuration. Low-voltage monitoring Input. Ground/No Connect. Can be grounded or left floating but do not connect to any other potentials. High-voltage monitoring input. It is also the internal-supply-voltage enabling input.
Rev. PrJ | Page 7 of 32
AD5100
V1MON OV Threshold 7.92 9.00 9.90 11.00 12.00 13.20 14.14 15.23 15.84 17.22 18.00* 18.86 19.80 22.00 24.75 28.29 V1MON UV Threshold 6.00 6.49 6.95 7.47 7.92 8.43* 9.00 9.43 9.90 10.42 11.00 11.65 12.00 12.38 13.20 13.66 V2MON ON Threshold 3.00 3.30 4.50 4.77 6.00 6.49 6.95 7.47* 7.92 8.43 9.00 9.43 9.90 15.23 19.80 24.75 V2MON OFF Threshold 3.00 3.30 4.50 4.77 6.00 6.49 6.95* 7.47 7.92 8.43 9.00 9.43 9.90 15.23 19.80
Rising Edge Trigger/Pseudo CAN Wake Up Mode
Preliminary Technical Data
Table 5a. Available Programmable-Threshold at TA = 25 oC (All values are typical ratings; see Table 2 for tolerances) V3MON Threshold 2.32 2.64 2.93 3.10 4.36* 4.65 4.75 4.97 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved V4MON Threshold Disabled* 0.86 1.15 1.37 1.43 1.66 2.30 3.10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
* Default. V1MON_OV must be > V1MON_UV. V2MON_OFF will be ignored if > V2MON_ON but V2MON_OFF cannot be = V2MON_ON.
Table 5b. Look Up Table of Programming Code versus Typical Thresholds Shown in Table 5a Code V1MON OV Threshold 18.00* 18.86 15.84 17.22 24.75 28.29 19.80 22.00 9.90 11.00 7.92 9.00 14.14 15.23 12.00 13.20 V1MON UV Threshold 8.43* 7.92 9.43 9.00 6.49 6.00 7.47 6.95 12.38 12.00 13.66 13.20 10.42 9.90 11.65 11.00 V2MON ON Threshold 7.47* 6.95 6.49 6.00 4.77 4.50 3.30 3.00 24.75 19.80 15.23 9.90 9.43 9.00 8.43 7.92 V2MON OFF Threshold 6.95* 7.47 6.00 6.49 4.50 4.77 3.00 3.30 19.80
Rising Edge Trigger/Pseudo CAN Wake Up Mode
V3MON Threshold 4.36* 4.65 4.75 4.97 2.32 2.64 2.93 3.10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
V4MON Threshold Disabled* 0.86 1.15 1.37 1.43 1.66 2.30 3.10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
9.90 15.23 9.00 9.43 7.92 8.43
Rev. PrJ | Page 8 of 32
Preliminary Technical Data
Table 6a. Available Programmable Hold Time and Delay (All values are typical ratings; see Table 2 for tolerances) t1SD_HOLD (ms) 0.07 20 40 60 80 100 150 200* * Default Table 6b. Look Up Table of Programming Code versus Typical Timings Shown in Table 6a Code 000 001 010 011 100 101 110 111 * Default t1SD_HOLD (ms) 200* 150 100 80 60 40 20 0.07 t1SD_DELAY (ms) 1200* 1000 800 400 200 100 50 0.07 t2SD_HOLD (ms) 10* 20 30 40 50 100 200 0.07 t2SD_DELAY (ms) 100* 50 200 400 800 1000 1200 0.07 tRS_HOLD (ms) 200* 150 100 50 30 15 1 0.1 tWD (ms) 1500* 2000 1250 1000 750 500 250 100 t1SD_DELAY (ms) 0.07 50 100 200 400 800 1000 1200* t2SD_HOLD (ms) 0.07 10* 20 30 40 50 100 200 t2SD_DELAY (ms) 0.07 50 100* 200 400 800 1000 1200 tRS_HOLD (ms) 0.1 1 15 30 50 100 150 200* tWD (ms) 100 250 500 750 1000 1250 1500* 2000
AD5100
Rev. PrJ | Page 9 of 32
AD5100
Preliminary Technical Data
are both disabling functions for the external devices. The differences are output levels and driving capabilities that will be described later. In some cases the SHDN and RESET may be used interchangeably. The WDI (Watchdog) and MR (Manual Reset) inputs also control RESET output for external digital processor. Figure 4 shows the general flow chart and Table 7 summarizes the AD5100 functions and features.
THEORY OF OPERATION
The AD5100 is a Programmable System Management IC that has four channels of monitoring inputs. Two inputs have high voltage (30V) capability. For example if the AD5100 is used in the automotive application, the V1MON (Monitoring Input 1) should be the battery and the V2MON should either be the ignition switch or the pseudo CAN bus wake up signal input. Two other inputs, V3MON and V4MON, are low voltage for 0.9V, 1.8V, 2.5V, 3.3V, or 5V monitoring. The two high voltage inputs control the shutdown signal, SHDN , while the two low voltage inputs control the reset signal, RESET . The SHDN and RESET
No
No
MR=1 SHDN=0*
yes
RESET=0
V1MON>UV
yes No
V1MONyes
SHDN=0*
Floating WDI Disabled
yes
No
No
Floating WDI
yes No (Advance WDI Selected)
V2MON Level Sensitive Selected
yes
No (V2MON Rising Edge Sensitive Selected)
Standard WDI Selected
yes No
RESET=0
No
Valid WDI
No
RESET=0
Valid WDI
yes
RESET=0 SHDN=0
V2MON>ON
yes No
SHDN=0
yes
V2MON>OFF
yes
SHDN=0
V3MON> Threshold
yes
No
RESET=0
SHDN=1
V4MON Disabled
yes
No
Using V4OUT for PWM
yes
No
V4MON> Threshold
yes
No
RESET=0
V4MON> Threshold
yes
No
V4OUT=0
V4OUT=1
Continue Monitoring
Default Paths
* See Table 9 RESET Configuration Register: If [0] = 0, then SHDN =0 and RESET = 0 If [0] = 1, then SHDN =0 and RESET = 1
Figure 4. General Flow Chart
Table 7. AD5100 Functions and Features
Input Monitoring Range 6 - 30 V 3 - 30 V 2.5 - 5.0 V 0.9 - 3.3 V 0-5V Shutdown Control Reset Cont rol
Rev. PrJ | Page 10 of 32
Fault Dete ction
Functions and Features
If Not Used
V1MON V2MON V3MON V4MON WDI
Over/Under Voltage On/Off Voltage CAN Bus Wake Up
Does not apply Tie to V1MON, Min Input Connect to VOTP and Threshold to Minimum
Additional Output Standard, Advance, or Watchdog Selectable
Select Disable in Threshold
Leave Floating
Preliminary Technical Data
MR
0-5V Highest Prority on Other Inputs
AD5100
Leave Floating
Monitoring Inputs
V1MON V1MON is a high-voltage monitoring input that controls the SHDN and RESET functions of the external devices. In addition, it also provides a shutdown warning to the system. V1MON monitors inputs from 6V to 30V. It has a 16-level programmable over-voltage, under-voltage (OV,UV) shutdown threshold with an 8-step 0.05ms-200ms shutdown hold time and 0.05ms-1200ms shutdown delay. The shutdown hold time means that the shutdown of the external device is held until the programmed-time is reached. On the other hand, the shutdown delay means that shuting down the external device is delayed until the programmed-time is reached. The OV threshold chosen must be greater than the UV threshold. When the shutdown is triggered either because the input has reached OV or UV threshold, such fault condition will be temporarily recorded in the Fault Detection Register. The SHDNWARN output will transition low for signaling before shutdown occurs. The occurance of Shutdown is
tGLITCH
depending on how long the shutdown programmed-delay is set relative to the SHDNWARN propagation delay, this feature attempts to allow the system to finish any critical house keeping tasks before shuting down the external device. The V1MON, shutdown, and shutdown warning timing diagrams are shown in Figure 5. The ranges of OV and UV Thresholds are shown in Table 5a and the programming codes of the selected-thresholds are found in Table 5b. The defaulted OV threshold is 18.00V and UV threshold is 8.43V. Simarily, the ranges of shutdown hold and delay times are shown in Table 6a and the programming codes of the selected-timings are found in Table 6b. The defaulted shutdown hold time is 200ms delay time is 1200ms. The voltage at V1MON provides the power for the AD5100 but valid signal at V2MON must be present before the internal VREG starts operation. Details will be explained in the power section.
V1MON_OV *
V1MON
V1MON_UV *
tGLITCH V2MON_ON *
V2MON
tMIN# t2SD_HOLD * t1SD_DELAY * t1SD_HOLD * t t1SD_HOLD * 1SD_DELAY * t2SD_DELAY * t2SD_HOLD * t2SD_DELAY *
V2MON_OFF *
SHDN
tFD_DELAY
tFD_DELAY
tFD_DELAY
tFD_DELAY
SHDNWARN
* = Programmable
#: The duration of the tMIN must be shorter than tVREG_Off_Delay or else the AD5100 will be powered off
Figure 5. V1MON and V2MON Shutdown Timing Diagrams (Note RESET follows SHDN ).
The V1MON pin is monitored by two comparators, one for over-voltage, and one for under-voltage detection. Both are designed with 1.5% hysteresis. When the V1MON n input goes above the programmed OV threshold, the comparator will become active immediately,
indicating an OV condition has occurred. Due to hysteresis, the V1MON input must be brought below the programmed OV threshold by 1.5% before the comparator will be in-active, indicating the OV condition has gone away, see Figure 6.
Rev. PrJ | Page 11 of 32
AD5100
When the V1MON input drops below the programmed UV threshold, the comparator will become active immediately, indicating a UV condition has occurred. Similarly due to hysteresis, the V1MON input must be brought above the programmed UV threshold by 1.5% before the comparator will be in-active, indicating the UV condition has gone away. Both V1mon comparators are used (in conjunction with hold and delay timers) to control the SHDN and RESET pins. V1MON exhibits typical input resistance of 60K that users should account the loading effect. The default V1MON OV and UV thresholds are 18.00V and 8.43V respectively. The default V1MON Shutdown Hold time and Shutdown Delay are 200ms and 1200ms respectively. User should refer to Tables 5b and 6b if they want to program different settings. V2MON V2MON is a high-voltage monitoring input that controls the SHDN and RESET functions of the external devices. V2MON monitors inputs from 3V to 30V. It has a 16-level programmable Turn-on, Turn-off (ON,OFF) hysteresis threshold with an 8-step 0.05ms-200ms shutdown hold time and 0.05ms-1200ms shutdown delay. By default, V2MON is level-sensitive that the ON and OFF thresholds are both monitored. The ON threshold chosen must be greater than the OFF threshold. When the shutdown function is triggered by the input reaching V2MON_OFF threshold, such fault condition will be temporarily recorded in the Fault Detection Register. The SHDNWARN output will transition low for signaling before shutdown occurs. The occurance of shutdown is depending on how long the shutdown programmed-delay is set relative to the SHDNWARN propagation delay, this feature attempts to allow the system to finish any critical house keeping tasks before shuting down the external device. The V2MON, shutdown, and shutdown warning pins timing diagrams are also shown in Figure 5. The ranges of ON and OFF Thresholds are shown in Tables 5a and the programming codes of the selectedthresholds are found in Table 5b. The defaulted ON threshold is 7.47V and OFF threshold is 6.95V. Simarily, the ranges of shutdown hold and delay times are shown in Table 6a and the programming codes of the selected-timings are found in Table 6b. The defaulted shutdown hold time is 10ms and delay time is 100ms. V2MON_OFF will be ignored if V2MON_OFF > V2MON_ON but V2MON_OFF cannot be = V2MON_ON. If the V2MON is selected with Rising Edge Triggered, only the ON threshold is monitored and the OFF Threshold is ignored. The voltage at V1MON provides the power for the AD5100 but valid signal at V2MON must be present before the internal VREG starts operation. Details will be explained in the power section.
V1MON_OV
Preliminary Technical Data
Hysteresis V1MON
V1MON_UV
Hysteresis
OV Comparator Active
OV Comparator In-Active UV Comparator Active UV Comparator In-Active
Figure 6. V1MON Hysteresis.
The V2MON pin is monitored by 2 comparators, 1 for turn-on, and 1 for turn-off detection in the level sensitive power-up mode. Both are designed with 1.5% hysteresis. On the other hand, the turn-on monitoring comparator is used only if the rising edge trigger power-up mode is selected. When the V2MON input goes above the programmed Ton threshold, the comparator will become active immediately, indicating an OV condition has occurred. Due to hysteresis, the V2MON input must be brought below the programmed threshold by 1.5% before the comparator will be in-active, indicating the OV condition has gone away, see Figure 7. When the V2MON input drops below the programmed threshold, the comparator will become active immediately, indicating a UV condition has occurred. Similarly due to hysteresis, the V2MON input must be brought above the programmed threshold by 1.5% before the comparator will be in-active, indicating the UV condition has gone away.
V2MON_ON Hysteresis
V2MON
V2MON_OFF
ON Comparator Active ON Comparator In-Active OFF Comparator Active OFF Comparator In-Active
Hysteresis
Figure 7. V2MON Hysteresis.
V2MON exhibits typical input resistance of 60K that users should account the loading effect. The default V2MON ON and OFF thresholds are 7.47V and 6.95V respectively. The default V2MON Shutdown Hold time and Shutdown Delay are 10ms and 100ms respectively. User should refer to Tables 5b and 6b if they want to program different settings.
Rev. PrJ | Page 12 of 32
Preliminary Technical Data
V3MON V3MON is a low-voltage monitoring input that controls the RESET function of an external device. V3MON monitors inputs from 2.5V to 5.5V. It has an 8-step programmable reset threshold with an 8-step 0.1ms-200ms reset hold time. The reset hold time means that the reset of the external device is held until the programmed-time is reached. The V3MON and reset timing diagrams are shown in Figure 8. The range of
tGLITCH V3MON
AD5100
thresholds is shown in Table 5a and the programming code of the selected-threshold is found in Table 5b. The defaulted monitoring threshold is 4.36V. Similarly, the range of reset hold time is shown in Tables 6a and the programming code of the selected-timing is found in Table 6b. The defaulted reset hold time is 200ms.
V3MON
tRS_HOLD*
tRS_DELAY
tRS_HOLD*
tRS_DELAY
RESET
* Programmable
Figure 8. V3MON RESET Timing Diagrams
The V3MON pin is monitored by a comparator to detect an under-voltage condition. It is designed with 1.5% hysteresis. When the V3MON input drops below the programmed UV threshold, the comparator will become active immediately, indicating a UV condition has occurred. Due to hysteresis, the V3MON input must be brought above the programmed UV threshold by 1.5% before the comparator will be in-active, indicating the UV condition has gone away, see Figure 9. The V3MON comparator is used (in conjunction with a hold timer) to control the RESET pin. V3MON exhibits typical input resistance of 50K that users should account the loading effect. The MR input has an internal resistor pull-up toV3MON. The RESET output are push-pull configured between V3MON and GND.
V3MON
V3MON_UV Hysteresis
UV Comparator In-Active
UV Comparator In-Active
Figure 9. V3MON Hysteresis.
The default V3MON threshold is 4.36V. User should refer to Table 5b if they want to program different setting.
V4MON V4MON is the lowest voltage monitoring input that controls the RESET function of an external device or provides a comparator output, V4OUT. V4MON monitors input from 0.9V to 3.3V. It has an 8-step programmable reset threshold with an 8-step 0.1ms to 200ms reset hold time. The V4MON, reset, and V4OUT timing diagrams are shown in Figure 10. The range of
thresholds is shown in Table 5a and the programming code of the selected-threshold is found in Tables 5b. The defaulted monitoring threshold is Disabled. Similarly, the range of reset hold time is shown in Tables 6a and the programming code of the selected-timing is found in Table 6b.
Rev. PrJ | Page 13 of 32
AD5100
tGLITCH V4MON
Preliminary Technical Data
V4MON
tRS_HOLD*
tRS_DELAY
tRS_HOLD*
tRS_DELAY
RESET
V4OUT
*Programmable Most Applications using V4OUT require disabling of V4MON triggered reset
Figure 10. V4MON , RESET , and V4OUT Timing Diagrams
The V4MON pin is monitored by a comparator to detect an under-voltage condition. It is designed with 6% hysteresis. When the V4MON input drops below the programmed UV threshold, the comparator will become active immediately, indicating a UV condition has occurred. Due to hysteresis, the V4MON input must be brought above the programmed UV threshold by 6% before the comparator will be in-active, indicating the UV condition has gone away, See Figure 11. The V4MON comparator is used to control the V4OUT pin and also (in conjunction with a hold timer) to control the RESET pin. V4MON exhibits typical input resistance of 50K that users should account the loading effect.
V4MON
V4MON_UV Hysteresis
UV Comparator In-Active
UV Comparator In-Active
Figure 11. V4MON Hysteresis.
The default V4MON is Disabled. User should refer to Table 5b if they want to program a different setting.
Rev. PrJ | Page 14 of 32
Preliminary Technical Data
Watchdog Input The Watch-Dog Input (WDI) circuit attempts to reset the system to a known good state if a software or hardware glitch renders the system processor inactive for a duration that is longer than the timeout period. There is an 8-step programmable timeout period from 100ms to 2000ms.The watchdog circuit is independent of the CPU clock that the watchdog is monitoring. Watchdog is disabled during power-up. WDI starts monitoring once the RESET is high. Unique to AD5100, it
tWDI
AD5100
provides a Standard or Advance Watchdog monitoring function. In the defaulted Standard Watchdog mode, if WDI remains either high or low for longer than the timeout period, a reset pulse is generated in an attempt to allow the system processor to re-establish the WDI signal. The reset pulses continue indefinitely until a valid watchdog signal, a rising or falling edge signal at the WDI, is received. The internal watchdog timer clears whenever reset is asserted. The Standard WDI and RESET timing diagrams are shown in Figure 12.
WDI
tWD tWDR
tWD tWDR
RESET
reset pulse Continuous pulses until WD awakes
Figure 12. Standard Watchdog - Pulsing Reset Until Watchdog Awakes.
On the other hand, the AD5100 can be programmed to an Advance Watchdog mode such that when the watchdog remains inactive longer than three times the watchdog timeout period, at the forth time the SHDN and RESET will be
tWDI
asserted and released after 1 second. These actions repeat indefinitely, unless it is interferred by the user, if the processor is not responding. The Advance WDI and RESET timing diagrams are shown in Figure 13.
WDI
tWD tWDR
tWD tWDR
RESET
1 reset pulse 3 reset pulses tWD_SHDN
SHDN
Shutdown at 4th reset pulse
Release after 1s
Figure 13. Advance Watchdog - SHDN Asserted After Three Trials of Reseting the Watchdog. SHDN Released After 1 second and the cycle repeats.
The range of Watchdog Timeout is shown in Table 6a and the programming code of the selected-timeout is found in Table 6b. The default timeout is 1500ms.
If WDI is floating, the watchdog is disabled by default. However, floating watchdog can be enabled through I2C
Rev. PrJ | Page 15 of 32
AD5100
programming such that a broken WDI connection or any unusual condition that makes WDI float will trigger the reset. Enabling or disabling floating WDI can be changed dynamically provided that the OTP fuse of such function is not programmed or the OTP overriden function is selected. Manual Reset Manual Reset MR is active low and it has an internal pull-up resistor to V3MON. MR can be driven from a CMOS logic signal. The MR and RESET timing diagrams are shown in
Preliminary Technical Data
The default Watchdog Timeout is 1500ms. User should refer to Table 6b if they want to program a different setting.
Figure 14. MR has the highest priority in triggering the RESET over any other monitoring inputs.
MR
< tMR_GLITCH tMR tMR_DELAY tRS_HOLD*
RESET
*Programmable
Figure 14. Manual Reset Timing Diagrams
Rev. PrJ | Page 16 of 32
Preliminary Technical Data
Outputs
Shutdown Generator The shutdown output, SHDN , is triggered by the abnormal inputs of V1MON or V2MON. It can also be the result of a failed watchdog input. SHDN control can also be asserted low by users through I2C programming at anytime. To be explicit, the shutdown generator asserts a logic-low SHDN signal based on the following conditions: 1. 2. 3. During power-up. When V1MON goes over or under the threshold, Figure 5. When V2MON is below the turn-on threshold during the rising edge or the turn-off threshold during the falling edge in the default level sensitive mode, Figure 5. When the external monitoring processor cannot issue the necessary WDI signal and an Advanced WDI mode is selected, Figures 8 and 9. I2C programmed-shutdown.
AD5100
Figure 15. Shutdown Output. # = I2C Selectable, * = Default.
Reset Generator The Reset output, RESET , is triggered by the abnormal input of V3MON or V4MON. RESET activation can also be the result of the processor that is not generating the proper watchdog signal or the Manual Reset is triggered. To be explicit, the Reset generator asserts a logic-low RESET signal based on the following conditions 1. 2. 3. 4. 5. 6. During power up When V3MON drops below the threshold, Figure 8. When V4MON drops below the threshold, Figure 10. When SHDN output is asserted, Figures 5 and 13. When the external monitoring processor cannot issue the necessary WDI signal, Figures 12 and 13. When MR is asserted, Figure 14.
4.
5.
The SHDN signal is released after the programmable hold time. The SHDN output is push-pull configured with I2C selectable rail voltage of either V1MON in default or internal VREG. Figure 15 shows the SHDN output configurations, Pulldown resistor R1 ensures SHDN is pulled to ground when the AD5100 is not powered. When AD5100 is powered, M2a and M2b are both on. M2a has relatively lower impedance than M2b and R1 that the SHDN remains low at shutdown. When the AD5100 settles, sw1 will be on. M1 is stronger than M2a that SHDN will be pulled to the rail that makes AD5100 out of the shutdown mode. The AD5100 is likely be used to monitor and control power regulators in some applications where some regulators have the input and enable pins next to each other in fine pitch that may pose reliability concern under some abnormal conditions. To prevent this may happen, the AD5100 shutdown output features a smart-load detection that ensures the shutdown to respond for maximum protection. For example, if the car battery has not been started for an extensive period of time and a resistive dendrite may have formed across the SHDN and the battery terminal (V1MON), the dendrite will be blown immediately as the M2a is designed with adequate current sinking capability and remains in the on position to offer such protection. In another situation where the SHDN pin may be hard-shorted to any sub-30V source, the short-circuit detector will open sw2 and therefore limit the current by the high impedance M2b.
The RESET signal is asserted and maintained except when it is triggered by the WDI that will be described in the watchdog section. The RESET signal is released after the programmable hold time. As shown in Figure 16, The RESET output is push-pull configured with the the rail voltage of V3MON.
Figure 16. Reset Output.
Rev. PrJ | Page 17 of 32
AD5100
Fault Detection with Shutdown Warning An early shutdown warning is available for the system processor to identify the source of failure and take appropriate action before shuting down the external devices. Whenever the voltage at V1MON is detected as over-voltage or under-voltage, or the voltage at V2MON falls below the threshold, SHDNWARN outputs a logic 0. If the processor sees a logic-low on this pin, the processor may issue an I2C read command to identify the cause of failure reported in the Fault Detect/Status Register. The processor may store the information in the external EEPROM as a record of failure history. V4OUT V4OUT is an open-drain output triggered by V4MON wth minimum propogation delay and the programmable delay does not apply. V4OUT can be used as a PWM control over an external device or used as a monitoring signal. Most applications using V4OUT require disabling V4MON triggered reset with an I2C command.
Preliminary Technical Data
Rev. PrJ | Page 18 of 32
Preliminary Technical Data
Power Requirements
Internal Power The AD5100 internal power VREG is derived from V1MON and V2MON is used to turn AD5100 on and off with a different behavior depending on the V2MON monitoring mode selection. By default, in the V2MON level sensitive mode, the AD5100 turns on when the voltage at V2MON rises above the logic threshold V2MON_ON, When V2MON falls below the logic
tGLITCH V2MON_ON * V2MON_ON * V2MON_OFF * 2.2V t2SD_HOLD * t2SD_DELAY * t2SD_HOLD * t2SD_DELAY * t2SD_DELAY * V2MON_OFF *
AD5100
threshold V2MON_OFF, AD5100 will trun off 2 seconds after
SHDN is deasserted. Note that AD5100 requries 5 us to start up and that V1MON must be applied before V2MON. The extension
of the AD5100 turn-off attempts to allow the system to complete any housekeeping tasks before the system is powered off. Figure 17 shows the defaulted V2MON and VREG waveforms.
V2MON
SHDN
tVREG_On_Delay
VREG
tVREG_Off_Delay
tVREG_Off_Delay
6V < V1MON < 30V * Programmable
Figure 17. Internal Power VREG versus V2MON Timing Diagrams (Default)
If the Pulse-Sensitive V2MON Mode is selected instead, the AD5100 will not turn off when V2MON returns to a logic low. In this mode, once the part has been powered on, it can only
be power-down by an I2C power down instruction or by eliminating the supply on V1MON pin. This feature is for the applications that use a wake up signal.
VOTP A 6V supply voltage is needed only during OTP fuse programming. This voltage should be provided by an external source during factory programming and should have 6V/200mA driving capability. The OTP programming duration depends on the numbers of programming fuses with maximum duration of 10ms. VOTP is not required for normal operation. The VOTP has dual functions, it is used for programming the non-volatile memory fuse arrays as well as serving as a compensation network for internal power stability. As a result, a bypass capacitor must be connected at VOTP pin at all times. A low ESR 10uF tantalum capacitor is recommended.
6V - 30V
V1MON V2MON
3V - 30V APPLY FOR OTP ONLY 6V C2 10F VOTP
AD5100
Figure 18. Power Supply Requirement
AD5100 achieves the OTP function through blowing internal fuses. Users should always apply the 6 V one-time program voltage requirement at the first fuse programming attempt. Failure to comply with this requirement may lead to a change in the fuse structures, rendering programming inoperable. Care should be taken when SCL and SDA are driven from a low voltage logic driver.
Rev. PrJ | Page 19 of 32
AD5100
Poor PCB layout introduces parasitic inductance that may affect the fuse programming voltage droop. Therefore, it is mandatory that a 10F tantalum capacitor be placed as close as possible to the VOTP pin. The value and the type of C2 chosen are important. It should provide both a fast response and larger supply current handling with minimum supply droop during programming, see Figure 18. accuracy drop
Preliminary Technical Data
Reverse Battery Protection Reverse battery protection can be provided by a regular diode if the battery monitoring accuracy can be relaxed. Otherwise, a 60V P-Ch Power MOSFET, like NDT2955, can be used. Because of the MOSFET internal diode, the battery will first conduct through P1's body diode, as soon as the voltage reaches its source terminal, the voltage divider provides adequate gate-tosource voltage to turn on P1 and the voltage drop across the FET will be negligible. The resistor divider values are chosen such that the P1's maximum VGS is not violated and the current drawn through the battery is only a few A.
Protection
Over-Current Protection
If the V1MON is shorted internally in the AD5100 to GND, the short-circuit protection kicks in and limits subsequent current to 150mA in normal operation or 50mA when the VOTP is executed.
Thermal Shutdown
EMI Protection For EMI protection, ferrite bead or EMC rated inductor such as DR331-7-103 can be used.
When the AD5100 junction temperature is near the junction temperature limit, it will automatically shutdown and cut out the power from V1MON. The part will resume operational when the device junction temperature returns to normal.
For automotive applications, proper external protections on the AD5100 are needed in order to ensure reliable operation. The V1MON will likely be used for battery monitoring. The V2MON will likely be used for ignition switch or other critical inputs. As a result, these inputs may need additional protections such as EMI, loaddump, and ESD protections. In addition, battery input also requires reverse battery protection and short circuit fuse protection, see Figure 19.
ESD Protection
Figure 19. Protection Circuits
It is common to require a contact rating of 8kV and a noncontact or air rating of 15kV ESD protection for the automotive electronics. As a result, a ESD rated protection device must be used such as MMBV27VCL, a dual 40W TVS (Transient Voltage Suppressor) at the V1MON and V2MON. Load Dump Protection A load dump is a severe overvoltage surge that occurs when the car battery is being disconnected from a spinning alternator and the resulting long-duration, high-voltage surge introduced into the supply line. As a result, external load dump protection is recommended. Typically the load dump overvoltage lasts for few hundreds millisecond and peaks at around 40V to 70V while current can be as high as 1A. As a result, a load dump rated TVS D1 and D2 such as SMCJ17 are used to handle the surge energy. A series R is an in-line current limiting resistor, it should be adequate to limit the current without significant drop and yet small enough to not affect the input monitoring
Rev. PrJ | Page 20 of 32
Preliminary Technical Data
Digital Interface
All programmable parameters are set through a 2-wire I2C protocol with read/write access to the registers. All programmable parameters can be set permanently by blowing the OTP fuses at users' factories. Analog Devices offers device programming software, which effectively replaces the need for external I2C controllers or host processors for OTP programming in the factories. SCL Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. External 1k-2.2k pull-up resistor is needed. The pull-up resistor should tie to V3MON if it is used to monitor a sub-5V source. SDA Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded first. External 1k-2.2k pull-up resistor is needed. The pull-up resistor should tie to V3MON if it is used to monitor a sub-5V source. AD0 I2C Slave Address Pin. AD5100 is a slave device that will communicate with a master if the AD0 bit in the protocol matches with the logic state of the AD5100's AD0 pin. Table 8 and Figure 20 show the example with two AD5100 devices operate on the same serial bus independently. Table 8. Slave Address Decoding Scheme AD0 AD0 Device Program Device Address ming Bit Pin ed 0 0V 0x2E (U1) 1 5V 0x2F (U2)
Rp Rp 5V
AD5100
SDA MASTER SCL
5V SDA SCL AD0 AD5100 U1 SDA SCL AD0 AD5100 U2
Figure 20. Two AD5100 Devices on One Bus
The master-device output bus-line drivers are open-drain pulldowns in a fully I2C compatible interface. AD5100 Register Map Table 9 outlines the Address Pointer Registers used to configure and control all parameters and functions in the AD5100. Table 10 shows the Address Pointer Register Structure. Table 9 also outlines if registers are writable, readable, or permanently settable. All registers are single-port, meaning they have the same address for read and write operations. The AD5100 ships from its manufacturing factory with default power-up values as listed in the last column. The user can experiment with different settings in the various threshold, delay and configuration registers. Once enough evaluation is done, the user can program their own power-up default values via a one time program (OTP) feature. When all desired settings have been programmed (or the user is satisfied with the manufacturers defaults), a lock-out bit can be set to prevent further/erroneous settings from being programmed. Some users will use the AD5100 as a `set and forget' device, i.e. program some default values and never need to change these over the life of the application. However some users will require `On the Fly' flexibility, i.e. the ability to change settings to values other than those they choose as their defaults. An additional feature of the AD5100 is the ability to temporarily over-ride the OTP executed settings and still allows users to program the parts dynamically in the field. All over-ride values will revert back to OTP executed settings once the AD5100 is power cycled. Register Writing, Reading, OTP & Over-Ride are explained later in the I2C section.
Rev. PrJ | Page 21 of 32
AD5100
Table 9. AD5100 Register Map Regi ster Add ress Re ad / W rit e R/ W Permane ntly settable
Preliminary Technical Data
Register Name & Bit Description Pre-OTP Power On Default (1)
0x01
Y
V1MON Over-Voltage Threshold [3:0] - 4 bits used to program V1MON OV Threshold [7:4] - Reserved
0x00 (18.00 V)
0x02
R/ W
Y
V1MON Under-Voltage Threshold [3:0] - 4 bits used to program V1MON UV Threshold [7:4] - Reserved
0x00 (8.43 V)
0x03
R/ W
Y
V2MON Turn-On Threshold [3:0] - 4 bits used to program V2MON TON Threshold [7:4] - Reserved
0x00 (7.47 V)
0x04
R/ W
Y
V2MON Turn-Off Threshold [3:0] - 4 bits used to program V2MON TOFF Threshold [7:4] - Reserved
0x00 (6.95 V)
0x05
R/ W
Y
V3MON RESET Threshold [2:0] - 3 bits used to program V3MON RESET Threshold [7:3] - Reserved
0x00 (4.36 V)
0x06
R/ W
Y
V4MON RESET Threshold [2:0] - 3 bits used to program V4MON RESET Threshold [7:3] - Reserved
0x00 (Disabled)
0x07
R/ W
Y
V1MON OV/UV Triggered SHDN Hold [2:0] - 3 bits used to program V1MON OV/UV Triggered SHDN Hold time [7:3] - Reserved
0x00 (200 mS)
0x08
R/ W
Y
V1MON OV/UV Triggered SHDN Delay [2:0] - 3 bits used to program V1MON OV/UV Triggered SHDN Delay time [7:3] - Reserved
0x00 (1200 mS)
0x09
R/ W
Y
V2MON Turn-On Triggered SHDN Hold [2:0] - 3 bits used to program V2MON TON Triggered SHDN Hold time [7:3] - Reserved
0x00 (10 mS)
0x0 A
R/ W
Y
V2MON Turn-Off Triggered SHDN Delay [2:0] - 3 bits used to program V2MON TOFF Triggered SHDN Delay time [7:3] - Reserved
0x00 (100 mS)
0x0
R/
Y
RESET Hold
Rev. PrJ | Page 22 of 32
0x00
Preliminary Technical Data
B W [2:0] - 3 bits used to program RESET Hold time [7:3] - Reserved 0x0 C R/W Y Watchdog Timeout [2:0] - 3 bits used to program Watchdog timeout time [7:3] - Reserved 0x0 D R/ W Y RESET Configuration [0] - 0 - RESET is active when SHDN is active 1 - RESET is not active when SHDN is active [1] - Reserved [2] - 0 - Enable V4MON over threshold to cause RESET 1 - Prevent V4MON over threshold to cause RESET (For V4OUT Application) [3] - 0 - Prevent floating WDI to cause RESET 1 - Enable floating WDI to cause RESET [7:4] - Reserved 0x0E R/ W Y SHDN Rail Voltage Configuration [2:0] - Reserved [3] - 0 - SHDN rail = V1MON 1 - SHDN rail = Vreg [7:4] - Reserved 0x0F R/ W Y Watchdog Mode [2:0] - Reserved [3] - 0 - Standard Mode 1 - Advanced Mode [7:4] - Reserved 0x15 R/ W Y Program Lock Fuse (Inhibit Further Programming) [2:0] - Reserved [3] - 0 - Fuse Programming allowed 1 - Fuse Programming Disabled [7:4] - Reserved 0x16 R/ W N Special Functions 1 [0] - 0 - OTP Enable A Inactive 1 - OTP Enable A Active [1] - 0 - OTP Enable B Inactive 1 - OTP Enable B Active [2] - 0 - Software assertion of SHDN Inactive
Rev. PrJ | Page 23 of 32
AD5100
(200 mS)
0x00 (1500 mS)
0x00
0x00
0x00
0x00
0x00
AD5100
1 - Software assertion of SHDN Active [3] - 0 - Over-ride of permanent settings Inactive 1 - Over-ride of permanent settings Active [7:4] - Reserved 0x17 R/ W N Special Functions 2
Preliminary Technical Data
0x00
[0] - 0 - Software Power-down of AD5100 Inactive 1 - Software Power-down of AD5100 Active(2) [7:1] - Reserved
0x18
R/ W
N
Disable Special Functions (3) [0] - 0 - Allow Over-ride Function 1 - Disable Further Over-ride Function [1] - 0 - Allow OTP Function 1 - Disable OTP Function [2] - 0 - Allow Manufacturer Test-modes 1 - Disable Manufacturer Test-modes [3] - 0 - Allow Software power-down Function 1 - Disable Software power-down Function [4] - 0 - Allow Software assertion of SHDN Function 1 - Disable Software assertion of SHDN Function [7:5] - Reserved
0x00
0x19
Ron ly
N
Fault Detect & Status Register [3:0] - These 4 level triggered bits indicate the current state of the comparators monitoring the V1MON and V2MON input pins. [0] - A `1' indicates V2MON input < V2MON OFF Threshold [1] - A `1' indicates V2MON input > V2MON ON Threshold [2] - A `1' indicates V1MON input < V1MON UV Threshold [3] - A `1' indicates V1MON input > V1MON OV Threshold [6:4] - These are Fault Detection bits can be decoded to indicate one or more conditions were present when a SHDN event occurred. These bits are edge triggered. 000 - None 001 - V1MON UV only 010 - V1MON OV only 011 - Never Occur 100 - V2MON Below OFF only 101 - V1MON UV AND V2MON Below OFF Both Occur 110 - V1MON OV AND V2MON Below OFF Both Occur
Rev. PrJ | Page 24 of 32
0x00
Preliminary Technical Data
111 - Never Occur [7] - Reserved
Notes 1. 2. 3.
AD5100
Values AD5100 has when shipped from manufacturer's factory. V2MON must be 0V for Software Power down. These register bits are set only. To clear them the AD5100 must be power cycled. In some cases the AD5100 may be connected to an I2C bus with lots of activity. Setting these bits is an added means of ensuring any erroneous activity on the bus does not cause AD5100 special functions to become active.
I2C Serial Interface
Control of the AD5100 is accomplished via an I C compatible serial bus. The AD5100 is connected to this bus as a slave device (the AD5100 has no master capabilities). The AD5100 has a 7-bit slave address. The six MSBs are 010111 and the LSB is determined by the state of the A0 pin. Therefore when A0 is low, the AD5100 slave address is 01011110 and 0101111 otherwise. Therefore the A0 pin allows the user to connect two AD5100s to the same I2C bus provided the two devices comply with the configurations shown in Figure 20. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when SDA goes from high-to-low while SCL is high. The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit which determines whether data is read from or written to the slave device Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL.
2
3.
When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a STOP condition. In the read mode, the master issues a no Acknowledge for the 9th clock pulse, (i.e., the SDA line remains high). The master then brings the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a STOP condition.
2.
For the AD5100, write operations contain either one or two bytes, while read operations contain one byte. The AD5100 makes use of an Address Pointer Register. The Address Pointer Register does not have and does not require an address, because it is the register to which the first data byte of every write operation is written automatically. This data byte is an address pointer that sets up one of the other registers for the second byte of the write operation or for a subsequent read operation. Table 10 shows the structure of the Address Pointer Register. Bits [6:0] signify the address of the register that is to be written to or read from. Bit [7] is used when OTP mode is invoked (use of this bit is explained later in the OTP section), and should be `0' for normal write/read operations.
Table 10 - Address Pointer Register Structure
Bit # Function [7] OTP En [6] AP6 [5] AP5 [4] AP4 [3] AP3 [2] AP2 [1] AP1 [0] AP0
Writing Data to AD5100
When writing data to the AD5100, the user begins by writing an address byte followed by the R/W bit set to `0'. The AD5100 will acknowledge (if the correct address byte is used) by pulling the SDA line low during the 9th clock pulse. The user then
SCL SDA 0 1 0 1 1 1 AD0 R/W
follows with two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second byte is the data to be written to the internal data register. After each byte the AD5100 acknowledges by pulling the SDA line low during the 9th clock pulse. Figure 21 illustrated this operation.
OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0
D7
D6
D5 D4
D3
D2
D1
D0 ACK. BY AD5100
ACK. BY AD5100 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 ADDRESS POINTER BYTE
ACK. BY AD5100 FRAME 3 DATA BYTE
03437-0-035
STOP BY MASTER
Rev. PrJ | Page 25 of 32
AD5100
Preliminary Technical Data
Figure 21 - Writing a register address to the Address Pointer Register, then writing data to the selected register
Reading Data from AD5100
When reading data from an AD5100 register there are two possibilities: 1. If the AD5100's Address Pointer Register value is unknown or not at the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the AD5100 as before, but only a value containing the register address is sent, because data is not
SCL SDA 0 1 0 1 1 1 AD0 R/W
to be written to the register. This is shown in Figure 22. A read operation is then performed consisting of the serial bus address, R/W bit set to `1', followed by the data byte
from the data register. This is shown in Figure 23.
2.
If the address pointer is known to be already at the desire address, data can be read from the corresponding data register without first writing to the Address Pointer Register.
OTP AP6 AP5 AP4 AP3 AP2 AP1 AP0 ACK. BY AD5100 FRAME 2 ADDRESS POINTER BYTE STOP BY MASTER
ACK. BY AD5100 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE
03437-0-035
Figure 22. Dummy Write to set proper Address Pointer.
SCL SDA 0 1 0 1 1 1 AD0 R/W
OTP D6 OK
D5
D4
D3
D2
D1
D0 NO ACK. BY MASTER
03437-0-037
ACK. BY AD5100 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 READ DATA BYTE
STOP BY MASTER
Figure 23. Read Data from the Address Pointer Register. Table 11 shows the read-back data byte structure. Bits [6:0] contain the data from the register just read. Bit [7] only has significance when OTP mode is being used, and should be ignored for normal read operations. The majority of AD5100's registers are 4-bits wide, with only the Status/FDR Register and disable Special Function Register by 7 bit and 5 bits wide respectively.
Table 11 - Read-Back Data Byte Structure
Bit # Function [7] OTP Okay [6] D6 [5] D5 [4] D4 [3] D3 [2] D2 [1] D1 [0] D0
Permanent Setting of AD5100 Registers (OTP Function)
When the user wants to permanently program settings to the AD5100, the one time program (OTP) function is invoked. To complete a permanent program cycle for a particular register, the following sequence should be used: 1. 2. 3. 4. Set bit [0] in register 0x16 using a normal write operation Set bit [1] in register 0x16 using a normal write operation Apply a 6V (200mA) voltage source to the OTP pin. This provides the current for the programming cycle. Write the desired permanent data to the register of choice, using a write operation with the OTP bit set to `1' in the Address Pointer byte.
minimum of 30ms for the AD5100 to perform the permanent setting of the internal register. The user has the opportunity to check whether the AD5100 programmed correctly by performing a read cycle, and monitoring the state of bit [7] (OTP Okay). OTP Okay = 1 indicates the AD5100 programmed correctly OTP Okay = 0 indicates the AD5100 programmed incorrectly Note: Read-back of the OTP Okay bit is only available for the read cycle following immediately after the program cycle. If a write or read of a different register is done immediately after the program cycle, then the opportunity for verifying if the programming was successful will have been missed. Figure 24 shows the recommended way of performing a program then read-back and verify of the V1MON Over-Voltage Register, (assuming steps 1-3 above have already been done).
When the write cycle has been completed, the user should allow
Rev. PrJ | Page 26 of 32
Preliminary Technical Data
Programming Sequence Comment S Start 0x5C Slave Addr ess + Write A Ack 0x01 Set V1MON OV Thres hold A Ack 0x8F OTP at setti ng 15 A Ack P Stop Delay Wait for 30ms
AD5100
S Start 0x5D Slave Addr ess + Read
Figure 24. Example of Executing OTP and a Successful Validation When all default registers have been programmed, the lock bit should be set. User programmed defaults won't become active until the first power cycle after the lock bit is set. Programming the lock bit is done in exactly the same manner as all other registers. To revert an over-ridden register back to its default setting, the following sequence should be used: 1. 2. Clear bit [3] in register 0x16 Write a dummy byte to the register of choice
Temporary Over-Ride of Default Settings (Over-Ride Function)
As stated previously in the register map section, even with the lock bit set, it is possible to temporarily over-ride the default values of any of the permanently programmable registers. To Over-Ride a permanent setting in a particular register, the following sequence should be used: 1. 2. Set bit [3] in register 0x16 (Special Functions 1) Write the desired temporary data to the register of choice
Clearing the Over-Ride bit in register 0x18 does not cause all overridden registers to revert back to their defaults at the same time. For example, imagine the user had over-ridden registers 0x01, 0x02 & 0x03. If the user now cleared the Over-Ride bit in register 0x16 and wrote a dummy byte to register 0x01, it would revert back to its default value. However registers 0x02 & 0x03 would still contain their Over-Ride data. To revert both registers back to their defaults, the user must write dummy data to each register individually. Power cycling the AD5100 will also revert all registers back to their programmed defaults.
While the Over-Ride bit is set in register 0x18, the user may override any registers they wish by simply writing to them with new data.
Controlling the AD5100
There are two ways to control the AD5100. Users can apply the AD5100 evaluation software for one time programming the devices in the factory without ever reprogramming the parts in
the fields. They can also design or make use of the on-board I2C controllers for programming the AD5100. The later is necessary for any dynamic or field programming applications.
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AD5100
Preliminary Technical Data
APPLICATIONS
Car Battery and Infotainment System Supply Monitoring
The AD5100 has two high-voltage monitoring inputs with shutdown and reset controls over external devices. For example, the V1MON and V2MON can be used to monitor the signals from a car battery and an ignition key in an automobile, respectively. Such application is shown in Figure 25. The shutdown output can be connected to the shutdown pin of an external regulator to prevent false conditions such as a weak battery or overcharging battery by an alternator. The reset output can be used to reset the processor in the event of a hardware or software malfunction. An example of the input and output responses of this circuit is shown in Figure 26.
Figure 25. Typical DSP in Car Infotainment Application.
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Preliminary Technical Data
OV
AD5100
Battery
UV
< tGLITCH
Ignition
tVREG_Off_Delay tVREG_On_Delay V2MON Off Shutdown
Vreg
UV Shutdown
SHDN
uP Failed Shutdown
+5V
+3.3V
WDI
MR
Shutdown Enable Reset +5V Brownout Reset uP Failed Reset Hi-Z WDI Reset Shutdown Enable Reset
RESET
Hi-Z
WDI Reset
MR Reset
Figure 26. Examples of SHDN and RESET Responses of circuit shown in Figure 25.
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AD5100
Battery Monitoring with Fan Control
V4MON can be used with V4OUT intandem to form a simple PWM control circuit. For example as shown in Figure 27, when a temperature sensor output connects to the V4MON input, with
Preliminary Technical Data
the proper threshold level set, V4OUT outputs high whenever the temperature goes above the threshold. This turns on the FET switch which activates the fan. When Vtemp drops below the threshold, V4OUT decreases which turns off the fan.
Vtemp TMP35
PA
Battery
VREG
SD
Vreg
Battery Ignition Vreg Vtemp /MR WDI
V1MON V2MON V3MON V4MON /MR
AD5100
SHDN
V4OUT
RESET WDI SD_WRN SCL SDA CLK
P
/MR WDI
MISO/MOSI
CLK
Figure 27. Power Amp Monitoring and Fan Control
VTEMP
V4MON Threshold
V4OUT
Note: V4MON reset disabled
Figure 28. V4OUT with respect to Vtemp withV4MON reset disabled in circuit shown in Figure 27.
Battery State of Charge Indicator and Shutdown Early Warning Monitoring
In the automotive application, the system designer may set the battery threshold to the lowest level in order to allow an automobile to start at the worst case condition. If the battery
AD5100
Ignition Battery
V2MON V1MON
remains at the low voltage level, it is indeed a poor battery. However, there is no way to warn the driver. As a result, the system designer may use V4OUT as the battery warning indicator. By stepping down the battery voltage monitored at V4MON, the LED is lit which gives a battery replacement warning. The circuit is shown in Figure 29.
SHDN
V4MON
V4OUT
SCL SDA SD_WRN
P
CLK
CLK
MISO/MOSI
Figure 29. Battery State of Charge Indication
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Preliminary Technical Data
Psuedo CAN Bus Wake Up Mode
Using the AD5100 as indicated in Figure 30, the microprocessor can control its own power down sequence using the CAN Bus wake up signal. The operator must select the last setting `Rising Edge Trigger/CAN wake up mode' in the V2MON Turn Off Threshold parameter (The I2C write command is S 01011100 A 00000100 A 00001001 A P). Now when the rising edge of the CAN Bus wake up signal is detected by V2MON, the AD5100 is powered up with shutdown pulls high. The external regulator is turned on to supply power to the microprocessor. A reset pulse train will be generated at the reset output if there is no watchdog activity. The pulse
AD5100
continues until the correct watchdog signal appears at the AD5100 WDI pin. The shutdown pin remains high as long as the AD5100 continues to receive the correct watchdog signal. When the microprocessor finishes its housekeeping tasks or powers down the software rountine, it stops sending a watchdog signal. In response, the AD5100 generates a reset. The shutdown pin will be pulled low 2 seconds after and the regulator output drops to 0V, which shuts down the microprocessor. At that point, the AD5100 goes into sleep mode.
Vi Vo
VREG
Battery CAN Wake Up Pulse(s)
V1MON SHDN SD
V2MON
AD5100
VDD
P
I/O I/O I/O
SCL SDA WDI RESET
RS
Figure 30. CAN Wake Up Mode
V2MON
WDI
RESET
SCL
SCL
SDA
SDA Write
SHDN
Notes *6V < V1MON < 30V *Select V2MON_OFF = Rising Edge Trigger/CAN wake up mode
Figure 31. CAN Bus operation of circuit shown in Figure 30.
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AD5100
Preliminary Technical Data
Figure 32. QSOP-16 Mechanical Dimension
ORDERING GUIDE
Model AD5100YRQZRL71 A AD5100YRQZ1 AD5100EVAL
1
Temperature Range -40C to +125C -40C to +125C
Package Code RQ-16 RQ-16
Package Description QSOP-16 QSOP-16 Evaluation Board
Full Container Quantity 1,000 98 1
Branding TBD TBD
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05692-0-2/06(PrJ)
Rev. PrJ | Page 32 of 32

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